Jobs · greenhouse:asteralabs
Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet
Asteralabs · San Jose, California, United States · Posted 5d ago
Available in 2 locations
San Jose, California, United States · onsite Apply → Taipei, Taiwan · onsite Apply →About the role
As a Principal/Senior Principal Design Verification Engineer, you will lead the verification strategy for complex IPs and SoC subsystems, focusing on CXL, PCIe, and Ethernet technologies. This role involves defining methodologies, mentoring teams, and ensuring successful silicon outcomes in AI and cloud infrastructure.
Read the full posting on greenhouse:asteralabs →
FAQ
Is the Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet role at Asteralabs remote?+
This Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet position is listed as onsite (San Jose, California, United States).
What seniority level is this Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet role?+
This is a lead level position.
How do I apply for the Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet role at Asteralabs?+
Use the "Apply on greenhouse:asteralabs" button to open the original posting on greenhouse:asteralabs, where you can submit your application directly to Asteralabs.