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RTL FPGA ASIC SOC Engineer
elsys-design · Cachan - 94 · Posted 11d ago
onsiteFull-timemid2-5 yrs40 - 45 k€ brut annuel🇫🇷 France
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About the role
La mission consiste à prendre en charge le design de plusieurs blocs d'un circuit intégré et/ou du top level. Les principaux objectifs du poste sont : - Participer à la définition des fonctions et de l’architecture, - Description des modules à réaliser, - Implémentation de la des...
Read the full posting on apec (posting in French) →
FAQ
Is the RTL FPGA ASIC SOC Engineer role at elsys-design remote?+
This RTL FPGA ASIC SOC Engineer position is listed as onsite (Cachan - 94).
What is the salary for the RTL FPGA ASIC SOC Engineer role at elsys-design?+
The listing states 40 - 45 k€ brut annuel.
What seniority level is this RTL FPGA ASIC SOC Engineer role?+
This is a mid level position.
How do I apply for the RTL FPGA ASIC SOC Engineer role at elsys-design?+
Use the "Apply on apec" button to open the original posting on apec, where you can submit your application directly to elsys-design.